1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a self-aligning photolithography method and a method of fabricating a semiconductor device using the same, in which a photolithography process is performed using a lower pattern without employing a separate mask.
2. Discussion of Related Art
A photoresist is a compound whose inner structure is changed when it is exposed to an energy such as light or heat. According to this characteristic, the photoresist is selectively exposed to light to form a specific pattern therein, being used in device fabrication processes, for example, etching or ion implantation. The principle factor in forming a fine pattern using photolithography is the wavelength of an exposure radiation source for exposing the photoresist. That is, the diffraction of light around a mask acts as the main limit factor for resolution. Diffraction of exposure radiation changes the size of the photoresist pattern. If diffracted rays of light are in contact with each other, the pattern is not formed.
There is explained below a conventional photolithography process with reference to the attached drawings. FIGS. 1A to 1F are cross-sectional views for explaining a conventional photolithography process using a negative photoresist.
In the conventional photolithography process, first of all, electrical parameters according to a circuit design are converted to physical sizes on a glass substrate using an emulsion, chrome and oxidized steel thin film, to form a photomask having a specific pattern. Thereafter, a pattern transfer process is carried out. That is, as shown in FIG. 1A, a to-be-etched layer 2 on a wafer 1 is cleaned and dried to be in the optimum state without having particles.
Referring to FIG. 1B, a photoresist 3 is coated on to-be-etched layer 2. Then, soft bake is performed in order to facilitate alignment of photomask and improve adhesion between to-be-etched layer 2 and photoresist 3, as shown in FIG. 1C. This soft bake process removes the solvent contained in photoresist 3. Referring to FIG. 1D, a photomask 4 is exactly aligned with wafer 1 and then exposed to ultraviolet rays to form polymerized portion(s). Here, the pattern of the polymerized portion of photoresist 3 varies depending on the type (positive or negative) of the photoresist 3. Specifically, with the positive type photoresist, the light-exposed portion of the photoresist is removed by the subsequent development. On the other hand, the light-exposed portion of the negative photoresist is left during the development.
Referring to FIG. 1E, photoresist 3 having the polymerized portion is developed to remove the portion of the photoresist 3 other than the polymerized portion, thereby forming a photoresist pattern 3a. Thereafter, as shown in FIG. 1F, the exposed portion of to-be-etched layer 2 is selectively etched using photoresist pattern 3a, thereby forming a layer pattern 2a. 
There is described below an example of a device fabrication process to which the aforementioned layer pattering in process is applied. FIG. 2 is a cross-sectional view of a xe2x80x9cstack via contactxe2x80x9d structure of a semiconductor device, which is typically applied to a multi-level metal line. Formation of this stack via contact requires exact alignment between a lower plug 21 and an upper plug 22. The process of forming the stack via contact is as follows. A first interlevel insulating layer 24 is formed on a wafer 23 on which a cell transistor (not shown) including an impurity diffusion region is formed, and selectively removed using a photomask to form a contact hole. Lower plug 21 is formed in the contact hole, and a second interlevel insulating layer 25 is formed on first interlevel insulating layer 24 including lower plug 21. A via contact hole is formed in second interlevel insulating layer 25 using a photomask, being exactly aligned with lower plug 21. The upper plug 22 is formed in the via contact hole. In the formation of the via contact, there is some alignment margin between lower and upper plugs 21 and 22. However, the alignment margin decreases as the device is highly integrated.
Another application of photolithography is a gate patterning process. FIG. 3 is a plan view showing a channeling effect according to gate channel width, and FIGS. 4A to 4D are cross-sectional views for explaining a gate fabrication process for restricting the channeling effect. As shown in FIG. 3, in a long channel gate, even if channeling effect occurs, it does not affect device characteristics. However, in a short channel gate, the channeling effect deteriorates the device characteristics.
The gate channeling occurs when impurities are implanted into portions of a substrate on both sides of the gate using a gate pattern, and a short channel is formed which allows the impurities to enter under the gate, thereby forming a channel without applying electrical signals. This channeling effect occurs if the channel width is defined in the size below the grain boundary size of a material layer for forming the gate, for example, a polysilicon layer. To restrict this channeling effect, there has been proposed a patterning and ion implanting method which is discussed below referring to FIGS. 4A-4D.
As shown in FIG. 4A, a gate oxide layer 42, polysilicon layer 43 and gate cap layer 44 are sequentially formed on a semiconductor substrate 41. As shown in FIG. 4B, polysilicon layer 43 and gate cap layer 44 are selectively patterned by photolithography, to form a gate pattern 45. As shown in FIG. 4C, LDD (Lightly Doped Drain) ion implantation is performed. Then, as shown in FIG. 4D, gate sidewall 46 are formed and ion implantation is executed for forming source and drain regions (not shown). Thereafter, gate cap layer 44 is removed from the gate electrode 45 and a silicide layer 47 is formed. With this process, the channeling effect according to ion implantation is restricted.
A conventional process of forming dual gates using photolithography is as follows. FIGS. 5A and 5B are cross-sectional views for showing etch profiles and unstable ion implanted regions. FIG. 5A shows that gate doping is carried out before etching of a gate forming material layer. In this case, the etch profile depends on the type of implanted impurity, n-type or p-type, resulting in unstable gate etching profile after the etch process for forming the gate is performed. FIG. 5B shows LDD ion implantation and source/drain ion implantation performed after gate patterning. In this case, although the etching profiles are stable, gate doping is not sufficiently performed because the ion implantation for forming the source and drain and the gate doping process are simultaneously executed.
There are the following problems associated with the above-described conventional photolithography and process of fabricating a semiconductor device using it. First of all, when the conventional photolithography is applied to the fabrication of stack via contact, which requires alignment of lower and upper layers, the misalignment of photomask occurs to deteriorate device characteristics. Secondly, in the case where a gate is patterned using the conventional photolithography and then ion implantation for forming source and drain regions is performed, if the gate is patterned to have a fine width below the grain boundary of a gate forming material, the channeling effect is inevitably provided. Furthermore, the process for restricting this channeling effect using the cap layer complicates the fabrication process.
Thirdly, when the gate is doped through pre-doping process before gate patterning during the formation of the dual gates, the gate layer is heavily doped and then etched. Thus, the gate etching profile depends on the type of impurity doped into the gate layer, thereby producing unstable etching profile. On the contrary, in the case where the gate forming layer is deposited and etched, and then the ion implantation process for forming the source and drain and the gate doping process are simultaneously performed, the simultaneous doping is carried out with doping condition for the source and drain, which results in insufficient gate doping.
Accordingly, the present invention is directed to a photolithography and method of fabricating a semiconductor device using the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a self-aligning photolithography method and method of fabricating a semiconductor device using the same, in which photolithography process is performed using a lower pattern without employing a separate mask.
To accomplish the objects of the present invention, there is provided a self-aligning photolithography method including the steps of forming a lower pattern layer on a semiconductor substrate, depositing a photoresist, and subjecting to exposure without a photomask such that the photoresist aligned with the lower pattern layer is not to be exposed by diffraction of light, and either removing or leaving only the photoresist aligned with the lower pattern layer by development.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.